It has been nearly 10 years since Hyper Transport released version 3.1. This protocol is still very much useful and very capable, but it's starting to age.
Feature of HT 3.1
- 32 Bit wide, but can be sub-devided into smaller widths
- Up to 41Gbps throughput (for 32bit), though most processors including AMD uses at most only half of this. (16 bit)
- Each pathway is bidirectional and is 5.2 GT/s per direction. QPI is 9.2 GT/s
- Seperated device to device connectivity, such as CPU to Memory, Video Card to Memory, Ethernet Card 1, to Ethernet Card 2
- External connectivity is allowed, therefore you can create a multi CPU environment with 2 boxes.
Future requests
- Up front the width should be increased in multiple stages to 128 or even larger. This would allow for greater multiple cocket compatibility, this would create a greater spead between the devices.
- Dynamic lane redistribution
- Second which would add to complexity, which be a Hyper Transport switch, this could allow for over committing the Lanes, especially when there are lanes that are under utilized, such as CPU to CPU links could be increased to almost all of 128bit for high CPU processing requirements, but once complete it releases all but the minimal required lanes.
- The biggest benefits with the increase lanes, is what the power can be reduced by lower then the speed, of each lane.
